hierodule_tim.c

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#include <hierodule_tim.h>
 
#ifdef HIERODULE_TIM_HANDLE_IRQ
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        typedef void (*T2V_Function_Pointer)(TIM_TypeDef*);
    #endif
#endif 
#ifdef __STM32F030x6_H 
static const uint32_t APB1_DIV1_SINGLE = (RCC_CFGR_PPRE_DIV1>>RCC_CFGR_PPRE_Pos);
#elif ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
static const uint32_t APB1_DIV1 = (RCC_CFGR_PPRE1_DIV1>>RCC_CFGR_PPRE1_Pos);
 
static const uint32_t APB2_DIV1 = (RCC_CFGR_PPRE2_DIV1>>RCC_CFGR_PPRE2_Pos);
#endif 
#ifdef HIERODULE_TIM_HANDLE_IRQ
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        static FUNC_POINTER UPD_Handler_TIM1 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM1 = NULL;
 
        static FUNC_POINTER CC2_Handler_TIM1 = NULL;
 
        static FUNC_POINTER CC3_Handler_TIM1 = NULL;
 
        static FUNC_POINTER CC4_Handler_TIM1 = NULL;
 
        static FUNC_POINTER BRK_Handler_TIM1 = NULL;
 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER UPD_Handler_TIM2 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC1_Handler_TIM2 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC2_Handler_TIM2 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC3_Handler_TIM2 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC4_Handler_TIM2 = NULL;
    #endif 
        static FUNC_POINTER UPD_Handler_TIM3 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM3 = NULL;
 
        static FUNC_POINTER CC2_Handler_TIM3 = NULL;
 
        static FUNC_POINTER CC3_Handler_TIM3 = NULL;
 
        static FUNC_POINTER CC4_Handler_TIM3 = NULL;
 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER UPD_Handler_TIM4 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC1_Handler_TIM4 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC2_Handler_TIM4 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC3_Handler_TIM4 = NULL;
    #endif 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER CC4_Handler_TIM4 = NULL;
    #endif 
        #ifdef __STM32F401xC_H 
        static FUNC_POINTER UPD_Handler_TIM5 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM5 = NULL;
 
        static FUNC_POINTER CC2_Handler_TIM5 = NULL;
 
        static FUNC_POINTER CC3_Handler_TIM5 = NULL;
 
        static FUNC_POINTER CC4_Handler_TIM5 = NULL;
 
        static FUNC_POINTER UPD_Handler_TIM9 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM9 = NULL;
 
        static FUNC_POINTER CC2_Handler_TIM9 = NULL;
 
        static FUNC_POINTER UPD_Handler_TIM10 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM10 = NULL;
 
        static FUNC_POINTER UPD_Handler_TIM11 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM11 = NULL;
 
        #elif defined __STM32F030x6_H 
        static FUNC_POINTER UPD_Handler_TIM14 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM14 = NULL;
 
        static FUNC_POINTER UPD_Handler_TIM16 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM16 = NULL;
 
        static FUNC_POINTER BRK_Handler_TIM17 = NULL;
 
        static FUNC_POINTER UPD_Handler_TIM17 = NULL;
 
        static FUNC_POINTER CC1_Handler_TIM17 = NULL;
 
        #endif
 
    #else 
        static FUNC_POINTER TIM1_CC_ISR            = NULL;
 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER TIM2_ISR               = NULL;
    #endif 
        static FUNC_POINTER TIM3_ISR               = NULL;
 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        static FUNC_POINTER TIM4_ISR               = NULL;
    #endif
 
        #ifdef __STM32F103xB_H 
        static FUNC_POINTER TIM1_UP_ISR            = NULL;
 
        static FUNC_POINTER TIM1_BRK_ISR           = NULL;
        #elif defined __STM32F401xC_H 
        static FUNC_POINTER TIM1_UP_TIM10_ISR      = NULL;
 
        static FUNC_POINTER TIM1_BRK_TIM9_ISR      = NULL;
 
        static FUNC_POINTER TIM5_ISR               = NULL;
 
        static FUNC_POINTER TIM1_TRG_COM_TIM11_ISR = NULL;
 
        #elif defined __STM32F030x6_H 
        static FUNC_POINTER TIM1_BRK_UP_TRG_COM_ISR = NULL;
 
        static FUNC_POINTER TIM14_ISR               = NULL;
 
        static FUNC_POINTER TIM16_ISR               = NULL;
 
        static FUNC_POINTER TIM17_ISR               = NULL;
 
        #endif
    #endif //HIERODULE_TIM_CONVENIENT_IRQ
#endif //HIERODULE_TIM_HANDLE_IRQ /** \endcond */
 
static const uint32_t TimerChannel_EN[7] =
{
    TIM_CCER_CC1E,
    TIM_CCER_CC2E,
    TIM_CCER_CC3E,
    TIM_CCER_CC4E,
    TIM_CCER_CC1NE,
    TIM_CCER_CC2NE,
    TIM_CCER_CC3NE
};
 
static const uint32_t TimerChannel_CCR[4] =
{
    offsetof(TIM_TypeDef, CCR1),
    offsetof(TIM_TypeDef, CCR2),
    offsetof(TIM_TypeDef, CCR3),
    offsetof(TIM_TypeDef, CCR4)
};
 
static uint32_t GetBaseFreq(TIM_TypeDef *Timer)
{
    volatile uint32_t BaseFreq;
    #ifdef __STM32F103xB_H 
    if(Timer != TIM1)
    {
        BaseFreq = (SystemCoreClock >>
            APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 
        if( (READ_REG(RCC->CFGR) & RCC_CFGR_PPRE1) != APB1_DIV1 )
        {
            BaseFreq *= 2;
        }
    }
    else
    {
        BaseFreq = (SystemCoreClock >>
            APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 
        if( (READ_REG(RCC->CFGR) & RCC_CFGR_PPRE2) != APB2_DIV1 )
        {
            BaseFreq *= 2;
        }
    }
    #elif defined __STM32F401xC_H 
    if(Timer != TIM1 && Timer != TIM9 && Timer != TIM10 && Timer != TIM11)
    {
        BaseFreq = (SystemCoreClock >>
            APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 
        if( (READ_REG(RCC->CFGR) & RCC_CFGR_PPRE1) != APB1_DIV1 )
        {
            BaseFreq *= 2;
        }
    }
    else
    {
        BaseFreq = (SystemCoreClock >> 
            APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 
        if( (READ_REG(RCC->CFGR) & RCC_CFGR_PPRE2) != APB2_DIV1 )
        {
            BaseFreq *= 2;
        }
    }
    #elif defined __STM32F030x6_H 
    BaseFreq = (SystemCoreClock >>
        APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]);
 
    if( (READ_REG(RCC->CFGR) & RCC_CFGR_PPRE) != APB1_DIV1_SINGLE )
    {
        BaseFreq *= 2;
    }
    #endif 
    BaseFreq /= (Timer->PSC+1);
    return BaseFreq;
}
 
static inline uint32_t *ChannelSelector(TIM_TypeDef *Timer, uint32_t ChannelOffset)
{
    return (uint32_t*)((char*)Timer + (size_t)ChannelOffset);
}
 
#ifdef HIERODULE_TIM_HANDLE_IRQ
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        static void Check_IT
        (
            TIM_TypeDef *Timer,
            FUNC_POINTER Handler,
            T2V_Function_Pointer ClearFlag
        )
        {
            if(Handler != NULL)
            {
                 Handler();
            }
            ClearFlag(Timer);
        }
 
        static void InfiniteLoopOfError(void)
        {
            while(1);
        }
    #endif
#endif 
void HIERODULE_TIM_SetPeriod(TIM_TypeDef *Timer, double DurationSec)
{
    WRITE_REG(Timer->ARR, GetBaseFreq(Timer)*DurationSec-1.0);
}
 
double HIERODULE_TIM_GetPeriod(TIM_TypeDef *Timer)
{
    return ((double)READ_REG(Timer->ARR)+1.0)/((double)GetBaseFreq(Timer));
}
 
void HIERODULE_TIM_SetFrequency(TIM_TypeDef *Timer, double Frequency_Hz)
{
    WRITE_REG(Timer->ARR, GetBaseFreq(Timer)/Frequency_Hz-1.0);
}
 
double HIERODULE_TIM_GetFrequency(TIM_TypeDef *Timer)
{
    return ((double)GetBaseFreq(Timer))/((double)(READ_REG(Timer->ARR)+1.0));
}
 
void HIERODULE_TIM_ClearCounter(TIM_TypeDef *Timer)
{
    Timer->CNT = 0U;
}
 
void HIERODULE_TIM_SetRepetition(TIM_TypeDef *Timer, uint32_t Reps)
{
    WRITE_REG(Timer->RCR, Reps);
}
 
uint32_t HIERODULE_TIM_GetRepetition(TIM_TypeDef *Timer)
{
    return READ_REG(Timer->RCR);
}
 
void HIERODULE_TIM_EnableChannel(TIM_TypeDef *Timer, int8_t Channel)
{
    if( (Channel > 0) && (Channel < 5) )
    {
        SET_BIT(Timer->CCER, TimerChannel_EN[Channel-1]);
    }
    else if( (Channel < 0) && (Channel > -4) )
    {
        SET_BIT(Timer->CCER, TimerChannel_EN[abs(Channel)+3]);
    }
}
 
void HIERODULE_TIM_DisableChannel(TIM_TypeDef *Timer, int8_t Channel)
{
    if( (Channel > 0) && (Channel < 5) )
    {
        CLEAR_BIT(Timer->CCER, TimerChannel_EN[Channel-1]);
    }
    else if( (Channel < 0) && (Channel > -4) )
    {
        CLEAR_BIT(Timer->CCER, TimerChannel_EN[abs(Channel)+3]);
    }
}
 
uint32_t HIERODULE_TIM_IsEnabledChannel(TIM_TypeDef *Timer, int8_t Channel)
{
    if( (Channel > 0) && (Channel < 5) )
    {
        if( (READ_BIT(Timer->CCER, TimerChannel_EN[Channel-1]))
            == (TimerChannel_EN[Channel-1]))
        {
            return 1UL;
        }
        else
        {
            return 0UL;
        }
    }
    else if( (Channel < 0) && (Channel > -4) )
    {
        if( (READ_BIT(Timer->CCER, TimerChannel_EN[abs(Channel)+3]))
            == (TimerChannel_EN[abs(Channel)+3]))
        {
            return 1UL;
        }
        else
        {
            return 0UL;
        }
    }
    else
    {
        return 0UL;
    }
}
 
void HIERODULE_TIM_EnableMainOutput(TIM_TypeDef *Timer)
{
    SET_BIT(Timer->BDTR, TIM_BDTR_MOE);
}
 
void HIERODULE_TIM_DisableMainOutput(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->BDTR, TIM_BDTR_MOE);
}
 
void HIERODULE_TIM_SetDutyCycle
(
    TIM_TypeDef *Timer,
    uint8_t Channel,
    double NormalizedDutyCycle
)
{
    if( (Channel > 0) && (Channel < 5) )
    {
        (*(ChannelSelector(Timer, TimerChannel_CCR[Channel-1]))) =
            ((uint32_t)(READ_REG(Timer->ARR)))*NormalizedDutyCycle;
    }
}
 
double HIERODULE_TIM_GetDutyCycle(TIM_TypeDef *Timer, uint8_t Channel)
{
    if( (Channel < 1) && (Channel > 4) )
    {
        return -1.0;
    }
    else
    {
        return
            ((double)(*(ChannelSelector(Timer, TimerChannel_CCR[Channel-1]))))
            / ((double)(READ_REG(Timer->ARR)));
    }
}
 
void HIERODULE_TIM_ClearFlag_UPD(TIM_TypeDef *Timer)
{
    WRITE_REG(Timer->SR, ~(TIM_SR_UIF));
}
 
void HIERODULE_TIM_ClearFlag_CC1(TIM_TypeDef *Timer)
{
    WRITE_REG(Timer->SR, ~(TIM_SR_CC1IF));
}
 
void HIERODULE_TIM_ClearFlag_CC2(TIM_TypeDef *Timer)
{
    WRITE_REG(Timer->SR, ~(TIM_SR_CC2IF));
}
 
void HIERODULE_TIM_ClearFlag_CC3(TIM_TypeDef *Timer)
{
    WRITE_REG(Timer->SR, ~(TIM_SR_CC3IF));
}
 
void HIERODULE_TIM_ClearFlag_CC4(TIM_TypeDef *Timer)
{
    WRITE_REG(Timer->SR, ~(TIM_SR_CC4IF));
}
 
void HIERODULE_TIM_ClearFlag_BRK(TIM_TypeDef *Timer)
{
    WRITE_REG(Timer->SR, ~(TIM_SR_BIF));
}
 
uint32_t HIERODULE_TIM_IsSetFlag_UPD(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsSetFlag_CC1(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsSetFlag_CC2(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsSetFlag_CC3(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsSetFlag_CC4(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsSetFlag_BRK(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
 
void HIERODULE_TIM_Enable_IT_UPD(TIM_TypeDef *Timer)
{
    HIERODULE_TIM_ClearFlag_UPD(Timer);
    SET_BIT(Timer->DIER, TIM_DIER_UIE);
}
 
void HIERODULE_TIM_Enable_IT_CC1(TIM_TypeDef *Timer)
{
    HIERODULE_TIM_ClearFlag_CC1(Timer);
    SET_BIT(Timer->DIER, TIM_DIER_CC1IE);
}
 
void HIERODULE_TIM_Enable_IT_CC2(TIM_TypeDef *Timer)
{
    HIERODULE_TIM_ClearFlag_CC2(Timer);
    SET_BIT(Timer->DIER, TIM_DIER_CC2IE);
}
 
void HIERODULE_TIM_Enable_IT_CC3(TIM_TypeDef *Timer)
{
    HIERODULE_TIM_ClearFlag_CC3(Timer);
    SET_BIT(Timer->DIER, TIM_DIER_CC3IE);
}
 
void HIERODULE_TIM_Enable_IT_CC4(TIM_TypeDef *Timer)
{
    HIERODULE_TIM_ClearFlag_CC4(Timer);
    SET_BIT(Timer->DIER, TIM_DIER_CC4IE);
}
 
void HIERODULE_TIM_Enable_IT_BRK(TIM_TypeDef *Timer)
{
    HIERODULE_TIM_ClearFlag_BRK(Timer);
    SET_BIT(Timer->DIER, TIM_DIER_BIE);
}
 
void HIERODULE_TIM_Disable_IT_UPD(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->DIER, TIM_DIER_UIE);
}
 
void HIERODULE_TIM_Disable_IT_CC1(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->DIER, TIM_DIER_CC1IE);
}
 
void HIERODULE_TIM_Disable_IT_CC2(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->DIER, TIM_DIER_CC2IE);
}
 
void HIERODULE_TIM_Disable_IT_CC3(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->DIER, TIM_DIER_CC3IE);
}
 
void HIERODULE_TIM_Disable_IT_CC4(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->DIER, TIM_DIER_CC4IE);
}
 
void HIERODULE_TIM_Disable_IT_BRK(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->DIER, TIM_DIER_BIE);
}
 
uint32_t HIERODULE_TIM_IsEnabled_IT_UPD(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE))
        ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsEnabled_IT_CC1(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE))
        ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsEnabled_IT_CC2(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE))
        ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsEnabled_IT_CC3(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE))
        ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsEnabled_IT_CC4(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE))
        ? 1UL : 0UL);
}
 
uint32_t HIERODULE_TIM_IsEnabled_IT_BRK(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE))
        ? 1UL : 0UL);
}
 
void HIERODULE_TIM_EnableAutomaticOutput(TIM_TypeDef *Timer)
{
    SET_BIT(Timer->BDTR, TIM_BDTR_AOE);
}
 
void HIERODULE_TIM_DisableAutomaticOutput(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->BDTR, TIM_BDTR_AOE);
}
 
void HIERODULE_TIM_EnableCounter(TIM_TypeDef *Timer)
{
    SET_BIT(Timer->CR1, TIM_CR1_CEN);
}
 
void HIERODULE_TIM_DisableCounter(TIM_TypeDef *Timer)
{
    CLEAR_BIT(Timer->CR1, TIM_CR1_CEN);
}
 
uint32_t HIERODULE_TIM_IsEnabledCounter(TIM_TypeDef *Timer)
{
    return ((READ_BIT(Timer->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
 
#ifdef HIERODULE_TIM_HANDLE_IRQ
 
#ifdef HIERODULE_TIM_CONVENIENT_IRQ 
void HIERODULE_TIM_Assign_ISR_UPD(TIM_TypeDef *Timer, FUNC_POINTER ISR)
{
    uint32_t TimerAddress = (uint32_t)Timer;
 
    switch(TimerAddress)
    {
        case ( (uint32_t)TIM1 ):
            UPD_Handler_TIM1 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM2 ):
            UPD_Handler_TIM2 = ISR;
            break;
        #endif 
        case ( (uint32_t)TIM3 ):
            UPD_Handler_TIM3 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM4 ):
            UPD_Handler_TIM4 = ISR;
            break;
        #endif
        #ifdef __STM32F401xC_H 
        case ( (uint32_t)TIM5 ):
            UPD_Handler_TIM5 = ISR;
            break;
        case ( (uint32_t)TIM9 ):
            UPD_Handler_TIM9 = ISR;
            break;
        case ( (uint32_t)TIM10 ):
            UPD_Handler_TIM10 = ISR;
            break;
        case ( (uint32_t)TIM11 ):
            UPD_Handler_TIM11 = ISR;
            break;
        #elif defined __STM32F030x6_H 
        case ( (uint32_t)TIM14 ):
            UPD_Handler_TIM14 = ISR;
            break;
        case ( (uint32_t)TIM16 ):
            UPD_Handler_TIM16 = ISR;
            break;
        case ( (uint32_t)TIM17 ):
            UPD_Handler_TIM17 = ISR;
            break;
        #endif 
        default:
            InfiniteLoopOfError();
    }
}
 
void HIERODULE_TIM_Assign_ISR_CC1(TIM_TypeDef *Timer, FUNC_POINTER ISR)
{
    uint32_t TimerAddress = (uint32_t)Timer;
 
    switch(TimerAddress)
    {
        case ( (uint32_t)TIM1 ):
            CC1_Handler_TIM1 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM2 ):
            CC1_Handler_TIM2 = ISR;
            break;
        #endif 
        case ( (uint32_t)TIM3 ):
            CC1_Handler_TIM3 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM4 ):
            CC1_Handler_TIM4 = ISR;
            break;
        #endif
        #ifdef __STM32F401xC_H 
        case ( (uint32_t)TIM5 ):
            CC1_Handler_TIM5 = ISR;
            break;
        case ( (uint32_t)TIM9 ):
            CC1_Handler_TIM9 = ISR;
            break;
        case ( (uint32_t)TIM10 ):
            CC1_Handler_TIM10 = ISR;
            break;
        case ( (uint32_t)TIM11 ):
            CC1_Handler_TIM11 = ISR;
            break;
        #elif defined __STM32F030x6_H 
        case ( (uint32_t)TIM14 ):
            CC1_Handler_TIM14 = ISR;
            break;
        case ( (uint32_t)TIM16 ):
            CC1_Handler_TIM16 = ISR;
            break;
        case ( (uint32_t)TIM17 ):
            CC1_Handler_TIM17 = ISR;
            break;
        #endif 
        default:
            InfiniteLoopOfError();
    }
}
 
void HIERODULE_TIM_Assign_ISR_CC2(TIM_TypeDef *Timer, FUNC_POINTER ISR)
{
    uint32_t TimerAddress = (uint32_t)Timer;
 
    switch(TimerAddress)
    {
        case ( (uint32_t)TIM1 ):
            CC2_Handler_TIM1 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM2 ):
            CC2_Handler_TIM2 = ISR;
            break;
        #endif 
        case ( (uint32_t)TIM3 ):
            CC2_Handler_TIM3 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM4 ):
            CC2_Handler_TIM4 = ISR;
            break;
        #endif
        #ifdef __STM32F401xC_H 
        case ( (uint32_t)TIM5 ):
            CC2_Handler_TIM5 = ISR;
            break;
        case ( (uint32_t)TIM9 ):
            CC2_Handler_TIM9 = ISR;
            break;
        #endif 
        default:
            InfiniteLoopOfError();
    }
}
 
void HIERODULE_TIM_Assign_ISR_CC3(TIM_TypeDef *Timer, FUNC_POINTER ISR)
{
    uint32_t TimerAddress = (uint32_t)Timer;
 
    switch(TimerAddress)
    {
        case ( (uint32_t)TIM1 ):
            CC3_Handler_TIM1 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM2 ):
            CC3_Handler_TIM2 = ISR;
            break;
        #endif 
        case ( (uint32_t)TIM3 ):
            CC3_Handler_TIM3 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM4 ):
            CC3_Handler_TIM4 = ISR;
            break;
        #endif
        #ifdef __STM32F401xC_H 
        case ( (uint32_t)TIM5 ):
            CC3_Handler_TIM5 = ISR;
            break;
        #endif 
        default:
            InfiniteLoopOfError();
    }
}
 
void HIERODULE_TIM_Assign_ISR_CC4(TIM_TypeDef *Timer, FUNC_POINTER ISR)
{
    uint32_t TimerAddress = (uint32_t)Timer;
 
    switch(TimerAddress)
    {
        case ( (uint32_t)TIM1 ):
            CC4_Handler_TIM1 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM2 ):
            CC4_Handler_TIM2 = ISR;
            break;
        #endif 
        case ( (uint32_t)TIM3 ):
            CC4_Handler_TIM3 = ISR;
            break;
        #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
        case ( (uint32_t)TIM4 ):
            CC4_Handler_TIM4 = ISR;
            break;
        #endif
        #ifdef __STM32F401xC_H 
        case ( (uint32_t)TIM5 ):
            CC4_Handler_TIM5 = ISR;
            break;
        #endif 
        default:
            InfiniteLoopOfError();
    }
}
 
void HIERODULE_TIM_Assign_ISR_BRK(TIM_TypeDef *Timer, FUNC_POINTER ISR)
{
    uint32_t TimerAddress = (uint32_t)Timer;
 
    switch(TimerAddress)
    {
        case ( (uint32_t)TIM1 ):
            BRK_Handler_TIM1 = ISR;
            break;
        #ifdef __STM32F030x6_H 
        case ( (uint32_t)TIM17 ):
            BRK_Handler_TIM17 = ISR;
            break;
        #endif 
        default:
            InfiniteLoopOfError();
    }
}
#else 
    void HIERODULE_TIM_Assign_TIM1_CC_ISR(FUNC_POINTER ISR)
    {
        TIM1_CC_ISR = ISR;
    }
 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
    void HIERODULE_TIM_Assign_TIM2_ISR(FUNC_POINTER ISR)
    {
        TIM2_ISR = ISR;
    }
    #endif 
    void HIERODULE_TIM_Assign_TIM3_ISR(FUNC_POINTER ISR)
    {
        TIM3_ISR = ISR;
    }
 
    #if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
    void HIERODULE_TIM_Assign_TIM4_ISR(FUNC_POINTER ISR)
    {
        TIM4_ISR = ISR;
    }
    #endif
    #ifdef __STM32F103xB_H 
    void HIERODULE_TIM_Assign_TIM1_UP_ISR(FUNC_POINTER ISR)
    {
        TIM1_UP_ISR = ISR;
    }
 
    void HIERODULE_TIM_Assign_TIM1_BRK_ISR(FUNC_POINTER ISR)
    {
        TIM1_BRK_ISR = ISR;
    }
    #elif defined __STM32F401xC_H 
    void HIERODULE_TIM_Assign_TIM1_UP_TIM10_ISR(FUNC_POINTER ISR)
    {
        TIM1_UP_TIM10_ISR = ISR;
    }
 
    void HIERODULE_TIM_Assign_TIM1_BRK_TIM9_ISR(FUNC_POINTER ISR)
    {
        TIM1_BRK_TIM9_ISR = ISR;
    }
 
    void HIERODULE_TIM_Assign_TIM5_ISR(FUNC_POINTER ISR)
    {
        TIM5_ISR = ISR;
    }
 
    void HIERODULE_TIM_Assign_TIM1_TRG_COM_TIM11_ISR(FUNC_POINTER ISR)
    {
        TIM1_TRG_COM_TIM11_ISR = ISR;
    }
 
    #elif defined __STM32F030x6_H 
    void HIERODULE_TIM_Assign_TIM1_BRK_UP_TRG_COM_ISR(FUNC_POINTER ISR)
    {
        TIM1_BRK_UP_TRG_COM_ISR = ISR;
    }
 
    void HIERODULE_TIM_Assign_TIM14_ISR(FUNC_POINTER ISR)
    {
        TIM14_ISR = ISR;
    }
 
    void HIERODULE_TIM_Assign_TIM16_ISR(FUNC_POINTER ISR)
    {
        TIM16_ISR = ISR;
    }
 
    void HIERODULE_TIM_Assign_TIM17_ISR(FUNC_POINTER ISR)
    {
        TIM17_ISR = ISR;
    }
    #endif
 
#endif //HIERODULE_TIM_CONVENIENT_IRQ /** \endcond */
 
#ifdef __STM32F103xB_H 
#if (HIERODULE_TIM_RESERVED != 1) 
extern void TIM1_UP_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
    Check_IT(TIM1, UPD_Handler_TIM1, &HIERODULE_TIM_ClearFlag_UPD);
    #else 
    TIM1_UP_ISR();
    #endif 
}
#endif
 
#elif defined __STM32F401xC_H 
#if ( (HIERODULE_TIM_RESERVED != 1) && (HIERODULE_TIM_RESERVED != 10) ) 
extern void TIM1_UP_TIM10_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
    if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM1) && HIERODULE_TIM_IsSetFlag_UPD(TIM1))
    {
        Check_IT(TIM1, UPD_Handler_TIM1, &HIERODULE_TIM_ClearFlag_UPD);
    }
    else if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM10) && HIERODULE_TIM_IsSetFlag_UPD(TIM10))
    {
        Check_IT(TIM10, UPD_Handler_TIM10, &HIERODULE_TIM_ClearFlag_UPD);
    }
    else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM10) && HIERODULE_TIM_IsSetFlag_CC1(TIM10))
    {
        Check_IT(TIM10, CC1_Handler_TIM10, &HIERODULE_TIM_ClearFlag_CC1);
    }
    #else 
    TIM1_UP_TIM10_ISR();
    #endif 
}
#endif
 
#endif  
#if (HIERODULE_TIM_RESERVED != 1) 
extern void TIM1_CC_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM1) && HIERODULE_TIM_IsSetFlag_CC1(TIM1))
        {
            Check_IT(TIM1, CC1_Handler_TIM1, &HIERODULE_TIM_ClearFlag_CC1);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC2(TIM1) && HIERODULE_TIM_IsSetFlag_CC2(TIM1))
        {
            Check_IT(TIM1, CC2_Handler_TIM1, &HIERODULE_TIM_ClearFlag_CC2);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC3(TIM1) && HIERODULE_TIM_IsSetFlag_CC3(TIM1))
        {
            Check_IT(TIM1, CC3_Handler_TIM1, &HIERODULE_TIM_ClearFlag_CC3);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC4(TIM1) && HIERODULE_TIM_IsSetFlag_CC4(TIM1))
        {
            Check_IT(TIM1, CC4_Handler_TIM1, &HIERODULE_TIM_ClearFlag_CC4);
        }
    #else 
        TIM1_CC_ISR();
    #endif 
}
 
#endif
 
#ifdef __STM32F103xB_H 
#if (HIERODULE_TIM_RESERVED != 1) 
extern void TIM1_BRK_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
    Check_IT(TIM1, BRK_Handler_TIM1, &HIERODULE_TIM_ClearFlag_BRK);
    #else 
    TIM1_BRK_ISR();
    #endif 
}
#endif
#elif defined __STM32F401xC_H 
#if ( (HIERODULE_TIM_RESERVED != 1) && (HIERODULE_TIM_RESERVED != 9) ) 
extern void TIM1_BRK_TIM9_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
    if(HIERODULE_TIM_IsEnabled_IT_BRK(TIM1) && HIERODULE_TIM_IsSetFlag_BRK(TIM1))
    {
        Check_IT(TIM1, BRK_Handler_TIM1, &HIERODULE_TIM_ClearFlag_BRK);
    }
    else if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM9) && HIERODULE_TIM_IsSetFlag_UPD(TIM9))
    {
        Check_IT(TIM9, UPD_Handler_TIM9, &HIERODULE_TIM_ClearFlag_UPD);
    }
    else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM9) && HIERODULE_TIM_IsSetFlag_CC1(TIM9))
    {
        Check_IT(TIM9, CC1_Handler_TIM9, &HIERODULE_TIM_ClearFlag_CC1);
    }
    else if(HIERODULE_TIM_IsEnabled_IT_CC2(TIM9) && HIERODULE_TIM_IsSetFlag_CC2(TIM9))
    {
        Check_IT(TIM9, CC2_Handler_TIM9, &HIERODULE_TIM_ClearFlag_CC2);
    }
    #else 
    TIM1_BRK_TIM9_ISR();
    #endif 
}
 
#endif
#elif defined __STM32F030x6_H 
#if (HIERODULE_TIM_RESERVED != 1) 
extern void TIM1_BRK_UP_TRG_COM_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
    if(HIERODULE_TIM_IsEnabled_IT_BRK(TIM1) && HIERODULE_TIM_IsSetFlag_BRK(TIM1))
    {
        Check_IT(TIM1, BRK_Handler_TIM1, &HIERODULE_TIM_ClearFlag_BRK);
    }
    else if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM1) && HIERODULE_TIM_IsSetFlag_UPD(TIM1))
    {
        Check_IT(TIM1, UPD_Handler_TIM1, &HIERODULE_TIM_ClearFlag_UPD);
    }
    #else 
    TIM1_BRK_UP_TRG_COM_ISR();
    #endif 
}
#endif
#endif 
#if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
#if (HIERODULE_TIM_RESERVED != 2) 
extern void TIM2_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM2) && HIERODULE_TIM_IsSetFlag_UPD(TIM2))
        {
            Check_IT(TIM2, UPD_Handler_TIM2, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM2) && HIERODULE_TIM_IsSetFlag_CC1(TIM2))
        {
            Check_IT(TIM2, CC1_Handler_TIM2, &HIERODULE_TIM_ClearFlag_CC1);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC2(TIM2) && HIERODULE_TIM_IsSetFlag_CC2(TIM2))
        {
            Check_IT(TIM2, CC2_Handler_TIM2, &HIERODULE_TIM_ClearFlag_CC2);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC3(TIM2) && HIERODULE_TIM_IsSetFlag_CC3(TIM2))
        {
            Check_IT(TIM2, CC3_Handler_TIM2, &HIERODULE_TIM_ClearFlag_CC3);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC4(TIM2) && HIERODULE_TIM_IsSetFlag_CC4(TIM2))
        {
            Check_IT(TIM2, CC4_Handler_TIM2, &HIERODULE_TIM_ClearFlag_CC4);
        }
    #else 
        TIM2_ISR();
    #endif 
}
#endif
#endif 
#if (HIERODULE_TIM_RESERVED != 3) 
extern void TIM3_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM3) && HIERODULE_TIM_IsSetFlag_UPD(TIM3))
        {
            Check_IT(TIM3, UPD_Handler_TIM3, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM3) && HIERODULE_TIM_IsSetFlag_CC1(TIM3))
        {
            Check_IT(TIM3, CC1_Handler_TIM3, &HIERODULE_TIM_ClearFlag_CC1);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC2(TIM3) && HIERODULE_TIM_IsSetFlag_CC2(TIM3))
        {
            Check_IT(TIM3, CC2_Handler_TIM3, &HIERODULE_TIM_ClearFlag_CC2);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC3(TIM3) && HIERODULE_TIM_IsSetFlag_CC3(TIM3))
        {
            Check_IT(TIM3, CC3_Handler_TIM3, &HIERODULE_TIM_ClearFlag_CC3);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC4(TIM3) && HIERODULE_TIM_IsSetFlag_CC4(TIM3))
        {
            Check_IT(TIM3, CC4_Handler_TIM3, &HIERODULE_TIM_ClearFlag_CC4);
        }
    #else 
        TIM3_ISR();
    #endif 
}
#endif 
#if ( (defined __STM32F103xB_H) || (defined __STM32F401xC_H) ) 
#if (HIERODULE_TIM_RESERVED != 4) 
extern void TIM4_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM4) && HIERODULE_TIM_IsSetFlag_UPD(TIM4))
        {
            Check_IT(TIM4, UPD_Handler_TIM4, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM4) && HIERODULE_TIM_IsSetFlag_CC1(TIM4))
        {
            Check_IT(TIM4, CC1_Handler_TIM4, &HIERODULE_TIM_ClearFlag_CC1);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC2(TIM4) && HIERODULE_TIM_IsSetFlag_CC2(TIM4))
        {
            Check_IT(TIM4, CC2_Handler_TIM4, &HIERODULE_TIM_ClearFlag_CC2);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC3(TIM4) && HIERODULE_TIM_IsSetFlag_CC3(TIM4))
        {
            Check_IT(TIM4, CC3_Handler_TIM4, &HIERODULE_TIM_ClearFlag_CC3);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC4(TIM4) && HIERODULE_TIM_IsSetFlag_CC4(TIM4))
        {
            Check_IT(TIM4, CC4_Handler_TIM4, &HIERODULE_TIM_ClearFlag_CC4);
        }
    #else 
        TIM4_ISR();
    #endif 
}
#endif
#endif 
#ifdef __STM32F401xC_H 
#if (HIERODULE_TIM_RESERVED != 5) 
extern void TIM5_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM5) && HIERODULE_TIM_IsSetFlag_UPD(TIM5))
        {
            Check_IT(TIM5, UPD_Handler_TIM5, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM5) && HIERODULE_TIM_IsSetFlag_CC1(TIM5))
        {
            Check_IT(TIM5, CC1_Handler_TIM5, &HIERODULE_TIM_ClearFlag_CC1);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC2(TIM5) && HIERODULE_TIM_IsSetFlag_CC2(TIM5))
        {
            Check_IT(TIM5, CC2_Handler_TIM5, &HIERODULE_TIM_ClearFlag_CC2);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC3(TIM5) && HIERODULE_TIM_IsSetFlag_CC3(TIM5))
        {
            Check_IT(TIM5, CC3_Handler_TIM5, &HIERODULE_TIM_ClearFlag_CC3);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC4(TIM5) && HIERODULE_TIM_IsSetFlag_CC4(TIM5))
        {
            Check_IT(TIM5, CC4_Handler_TIM5, &HIERODULE_TIM_ClearFlag_CC4);
        }
    #else 
        TIM5_ISR();
    #endif 
}
#endif 
#if ( (HIERODULE_TIM_RESERVED != 1) && (HIERODULE_TIM_RESERVED != 11) ) 
extern void TIM1_TRG_COM_TIM11_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM11) && HIERODULE_TIM_IsSetFlag_UPD(TIM11))
        {
            Check_IT(TIM11, UPD_Handler_TIM11, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM11) && HIERODULE_TIM_IsSetFlag_CC1(TIM11))
        {
            Check_IT(TIM11, CC1_Handler_TIM11, &HIERODULE_TIM_ClearFlag_CC1);
        }
    #else 
        TIM1_TRG_COM_TIM11_ISR();
    #endif 
}
 
#endif
#elif defined __STM32F030x6_H 
#if (HIERODULE_TIM_RESERVED != 14) 
extern void TIM14_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM14) && HIERODULE_TIM_IsSetFlag_UPD(TIM14))
        {
            Check_IT(TIM14, UPD_Handler_TIM14, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM14) && HIERODULE_TIM_IsSetFlag_CC1(TIM14))
        {
            Check_IT(TIM14, CC1_Handler_TIM14, &HIERODULE_TIM_ClearFlag_CC1);
        }
    #else 
        TIM14_ISR();
    #endif 
}
#endif 
#if (HIERODULE_TIM_RESERVED != 16) 
extern void TIM16_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM16) && HIERODULE_TIM_IsSetFlag_UPD(TIM16))
        {
            Check_IT(TIM16, UPD_Handler_TIM16, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM16) && HIERODULE_TIM_IsSetFlag_CC1(TIM16))
        {
            Check_IT(TIM16, CC1_Handler_TIM16, &HIERODULE_TIM_ClearFlag_CC1);
        }
    #else 
        TIM16_ISR();
    #endif 
}
#endif 
#if (HIERODULE_TIM_RESERVED != 17) 
extern void TIM17_IRQHandler(void)
{
    #ifdef HIERODULE_TIM_CONVENIENT_IRQ 
        if(HIERODULE_TIM_IsEnabled_IT_BRK(TIM17) && HIERODULE_TIM_IsSetFlag_BRK(TIM17))
        {
            Check_IT(TIM17, BRK_Handler_TIM17, &HIERODULE_TIM_ClearFlag_BRK);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_UPD(TIM17) && HIERODULE_TIM_IsSetFlag_UPD(TIM17))
        {
            Check_IT(TIM17, UPD_Handler_TIM17, &HIERODULE_TIM_ClearFlag_UPD);
        }
        else if(HIERODULE_TIM_IsEnabled_IT_CC1(TIM17) && HIERODULE_TIM_IsSetFlag_CC1(TIM17))
        {
            Check_IT(TIM17, CC1_Handler_TIM17, &HIERODULE_TIM_ClearFlag_CC1);
        }
    #else 
        TIM17_ISR();
    #endif 
}
#endif 
#endif
#endif